The present disclosure relates to dynamic random access memory (DRAM) devices with hierarchical bitlines.
As the feature size of DRAMs shrinks further, the bitlines for addressing the DRAM memory cells are also becoming shorter in order to maintain a low ratio of bitline parasitic capacitance to cell capacitance of the DRAM memory cell. Thus, it has become a technical challenge to route the shorter bitlines to the sense amplifiers that are used to detect the data stored in the cell capacitances of the DRAM memory cells.